CPC G11C 16/3481 (2013.01) [G06F 18/214 (2023.01); G06N 20/10 (2019.01); G11C 16/08 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 16/3404 (2013.01)] | 19 Claims |
1. A non-volatile memory device comprising:
a memory cell array comprising memory cells;
a page buffer circuit comprising page buffers respectively connected to bit lines;
a buffer memory; and
a control logic configured to:
obtain valley search detection information including read target block information and word line information by performing a valley search sensing operation on a distribution of threshold voltages of the memory cells,
obtain a plurality of read levels using a read information model by inputting the valley search detection information into the read information model, and
perform a main sensing operation for a read operation based on the plurality of read levels,
wherein the read information model is trained using a machine learning model by inputting the valley search detection information into the machine learning model, and the read information model infers the plurality of read levels for reading data from the memory cells.
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