US 11,670,385 B2
Method for writing an electrically erasable and programmable non volatile memory and corresponding integrated circuit
François Tailliet, Fuveau (FR); and Chama Ameziane El Hassani, Aix en Provence (FR)
Assigned to STMicroelectronics (Rousset) SAS, Rousset (FR)
Filed by STMicroelectronics (Rousset) SAS, Rousset (FR)
Filed on Dec. 21, 2021, as Appl. No. 17/558,123.
Application 17/558,123 is a continuation of application No. 16/824,268, filed on Mar. 19, 2020, granted, now 11,238,944.
Claims priority of application No. 1903667 (FR), filed on Apr. 5, 2019.
Prior Publication US 2022/0115077 A1, Apr. 14, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/32 (2006.01); G11C 16/10 (2006.01)
CPC G11C 16/32 (2013.01) [G11C 16/10 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for writing to an electrically erasable and programmable non-volatile memory, the method comprising:
operatively connecting a filter circuit belonging to a communication interface to an oscillator circuit, wherein the communication interface is physically connected to a bus, and wherein operatively connecting the filter circuit comprises transitioning the filter circuit from a disabled state to an enabled state, the enabled state comprising enabling access to functions of the filter circuit, the disabled state comprising a bypass mode corresponding to the filter circuit being non-operational and the oscillator circuit receiving a valid signal;
generating, by the oscillator circuit, an oscillation signal by accumulating elementary delays; and
regulating the oscillation signal by the filter circuit to generate a clock signal for timing a write cycle, the regulating comprising inserting an additional delay equal to a time constant of the filter circuit into the accumulation of elementary delays, the accumulation of elementary delays being negligible in duration with respect to the additional delay.