US 11,670,380 B2
Two-sided adjacent memory cell interference mitigation
Eran Sharon, Rishon Lezion (IL); Idan Alrod, Herzliya (IL); and Alexander Bazarsky, Holon (IL)
Assigned to SanDisk Technologies LLC, Addison, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Dec. 7, 2020, as Appl. No. 17/114,256.
Prior Publication US 2022/0180940 A1, Jun. 9, 2022
Int. Cl. G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 11/56 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/34 (2006.01); H01L 23/00 (2006.01); H01L 27/11582 (2017.01); H01L 25/065 (2023.01)
CPC G11C 16/26 (2013.01) [G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/3459 (2013.01); H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 27/11582 (2013.01); H01L 2224/08145 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06562 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a control circuit configured to connect to first non-volatile memory cells connected to a first word line, second non-volatile memory cells connected to a second word line adjacent to the first word line, and third non-volatile memory cells connected to a third word line adjacent to the first word line, the control circuit configured to:
apply two or more read reference voltages to the first word line along with two or more read pass voltages to the second word line for each of the two or more read reference voltages, wherein the two or more read reference voltages are associated with a same data state; and
determine a condition for each respective first memory cell based on sensing the respective first memory cell for a combination of a first voltage from the two or more read reference voltages that depends on a state of an adjacent cell on the third word line and a second voltage from the two or more read pass voltages that depends on a state of an adjacent cell on the second word line.