| CPC G11C 16/24 (2013.01) [G11C 16/0483 (2013.01); H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2224/08145 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01)] | 20 Claims |
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1. A nonvolatile memory device comprising:
a memory cell array formed in a first semiconductor layer and including a first memory cell and a second memory cell, the first memory cell being connected to a first word line and a first bit line, and the second memory cell being connected to the first word line and a second bit line;
a page buffer circuit formed in a second semiconductor layer located below the first semiconductor layer in a first direction, the page buffer circuit including a first page buffer and a second page buffer, the first page buffer being connected to the first bit line through a first through electrode passing through the first semiconductor layer and the second semiconductor layer in the first direction, and the second page buffer being connected to the second bit line through a second through electrode passing through the first semiconductor layer and the second semiconductor layer in the first direction; and
a page buffer controller formed in the second semiconductor layer and configured to control the first page buffer and the second page buffer to respectively detect data values respectively stored in the first memory cell and the second memory cell, wherein a develop timing of a first sensing node of the first page buffer is different from a develop timing of a second sensing node of the second page buffer,
wherein the first page buffer is closer to a through electrode region of the second semiconductor layer than the second page buffer, the through electrode region having the first through electrode and the second through electrode provided therein.
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