CPC G11C 16/10 (2013.01) [G11C 7/1048 (2013.01); G11C 16/0433 (2013.01); G11C 16/08 (2013.01); G11C 16/28 (2013.01); G11C 16/30 (2013.01); G11C 16/3404 (2013.01)] | 20 Claims |
1. A three-dimensional (3D) memory device, comprising:
a first set of memory layers, a second set of memory layers above the first set of memory layers, and a first dummy memory layer between the first and second sets of memory layers;
a plurality of NAND memory strings each extending through the first and second sets of memory layers and the first dummy memory layer; and
a peripheral circuit configured to sequentially program each memory layer of the first set of memory layers, and then sequentially program each memory layer of the second set of memory layers,
wherein the peripheral circuit comprises a word line (WL) driving circuit configured to:
when programming a first memory layer of the first set of memory layers, apply a first pre-charge voltage to the first dummy memory layer during a pre-charge period associated with the first memory layer; and
when programming a second memory layer of the first set of memory layers located above the first memory layer, apply a second pre-charge voltage to the first dummy memory layer during a pre-charge period associated with the second memory layer, the first pre-charge voltage being larger than the second pre-charge voltage.
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