US 11,670,361 B2
Sequential delay enabler timer circuit for low voltage operation for SRAMs
Moon-Hae Son, San Jose, CA (US); and Niranjan Behera, San Ramon, CA (US)
Assigned to Synopsys, Inc., Mountain View, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Jul. 15, 2021, as Appl. No. 17/377,080.
Claims priority of provisional application 63/052,354, filed on Jul. 15, 2020.
Prior Publication US 2022/0020420 A1, Jan. 20, 2022
Int. Cl. G11C 11/4094 (2006.01); G11C 11/408 (2006.01); G11C 11/4076 (2006.01); H03K 19/017 (2006.01); G11C 11/4091 (2006.01); G11C 16/34 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/4085 (2013.01) [G11C 11/4076 (2013.01); G11C 11/4091 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01); G11C 16/3404 (2013.01); H03K 19/01742 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a memory cell array coupled to a bitline and a first wordline; and
an NMOS pull-down structure coupled to the bitline and a plurality of PMOS transistors,
wherein:
the plurality of PMOS transistors is coupled to a second wordline, a logic value carried on the second wordline based on a logic value carried on the first wordline, and structured to pre-charge a plurality of drains of the NMOS pull-down structure to a high logic value based on a low logic value carried on the second wordline, and
the NMOS pull-down structure discharges the bitline based on a high logic value carried on the second wordline.