CPC G11C 11/4085 (2013.01) [G11C 5/06 (2013.01); G11C 11/4074 (2013.01); G11C 11/4094 (2013.01); G11C 11/4099 (2013.01)] | 20 Claims |
1. An integrated circuit comprising:
a cell array comprising a plurality of memory cells in a plurality of first columns and a plurality of word line assist cells in at least one second column;
a plurality of word lines respectively extending on a plurality of first rows of the cell array and connected to the plurality of memory cells and the plurality of word line assist cells;
at least one pseudo bit line respectively extending on the at least one second column and comprising a first pseudo bit line; and
a row driver configured to drive the plurality of word lines,
wherein each of the plurality of word line assist cells is configured to accelerate activation of respective ones of the plurality of word lines based on a voltage of the at least one pseudo bit line, comprises transistors that are identical to those of each of the plurality of memory cells, and has a footprint identical to that of each of the plurality of memory cells.
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