CPC G11C 11/4076 (2013.01) [G11C 11/4082 (2013.01); G11C 11/4087 (2013.01); G11C 11/4096 (2013.01)] | 16 Claims |
1. A latency setting circuit, comprising:
a clock driving circuit configured to delay a first operating clock by a latency corresponding to an activated one of a plurality of mode selection signals for setting different latencies to generate a first trigger signal, during a first operation; and
a first latency circuit configured to delay a first operating command and latch the first operating command according to the first trigger signal provided from the clock driving circuit to output a first internal command.
|