CPC G11C 11/4076 (2013.01) [H01L 25/0657 (2013.01); H01L 2225/06541 (2013.01)] | 20 Claims |
1. A memory die, comprising:
first circuitry coupled to a through-silicon via (TSV) that is configured to transmit signals to or receive signals from the memory die, the first circuitry configured to introduce propagation delay onto first signals transmitted to or received from the TSV at only the memory die; and
second circuitry configured, based at least in part on internal timings of second signals transmitted to or received from the TSV at another memory die, to adjust the propagation delay by activating the first circuitry, deactivating the first circuitry, or adjusting the first circuitry.
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