US 11,670,356 B2
Apparatuses and methods for refresh address masking
Yoshinori Fujiwara, Boise, ID (US); Harish V. Gadamsetty, Allen, TX (US); Gary Howe, Allen, TX (US); Dennis G. Montierth, Meridan, ID (US); Michael A. Shore, Boise, ID (US); and Jason M. Johnson, Nampa, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Jul. 16, 2021, as Appl. No. 17/305,878.
Prior Publication US 2023/0020753 A1, Jan. 19, 2023
Int. Cl. G11C 11/406 (2006.01); G11C 11/408 (2006.01); G11C 29/44 (2006.01); G11C 29/00 (2006.01); G11C 29/12 (2006.01)
CPC G11C 11/40622 (2013.01) [G11C 11/4085 (2013.01); G11C 11/4087 (2013.01); G11C 29/4401 (2013.01); G11C 29/787 (2013.01); G11C 2029/1202 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a fuse latch configured to store a selected address;
a refresh address generator configured to generate a refresh address as part of an application operation, wherein the refresh address is associated with a plurality of word lines;
a section decoder configured to generate a section enable signal based on the refresh address;
a comparator configured to provide a refresh stop signal at an active level if the selected address matches the refresh address;
a logic circuit configured to pass the section enable signal if the refresh stop signal is inactive and configured to suppress the section enable signal if the refresh stop signal is active; and
a row decoder configured to refresh a word line associated with the refresh address if the refresh stop signal is inactive and configured to not refresh the word line if the refresh stop signal is active, wherein all of the plurality of word lines are not refreshed if the refresh stop signal is active.