CPC G11C 11/40615 (2013.01) [G11C 11/4076 (2013.01); G11C 11/4096 (2013.01); G11C 11/40618 (2013.01)] | 20 Claims |
1. An accelerator comprising:
a signal control/monitoring circuit configured to detect an entry to a self-refresh mode of a memory device and an exit from the self-refresh mode based on monitoring a signal provided from a host;
an accelerator logic configured to generate a first command/address signal and a first piece of data; and
a selector configured to output the first command/address signal and the first piece of data to the memory device based on detection of the entry to the self-refresh mode, and output a second command/address signal and a second piece of data provided from the host to the memory device, based on detection of the exit from the self-refresh mode.
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