US 11,670,355 B2
Accelerator controlling memory device, computing system including accelerator, and operating method of accelerator
Minsu Kim, Seongnam-si (KR); Namhyung Kim, Seoul (KR); Daejeong Kim, Seoul (KR); Dohan Kim, Hwaseong-si (KR); Chanik Park, Seongnam-si (KR); Deokho Seo, Suwon-si (KR); Wonjae Shin, Seoul (KR); Changmin Lee, Hwaseong-si (KR); Ilguy Jung, Hwaseong-si (KR); and Insu Choi, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Aug. 19, 2021, as Appl. No. 17/406,511.
Claims priority of application No. 10-2021-0001476 (KR), filed on Jan. 6, 2021.
Prior Publication US 2022/0215871 A1, Jul. 7, 2022
Int. Cl. G11C 7/00 (2006.01); G11C 11/406 (2006.01); G11C 11/4076 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/40615 (2013.01) [G11C 11/4076 (2013.01); G11C 11/4096 (2013.01); G11C 11/40618 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An accelerator comprising:
a signal control/monitoring circuit configured to detect an entry to a self-refresh mode of a memory device and an exit from the self-refresh mode based on monitoring a signal provided from a host;
an accelerator logic configured to generate a first command/address signal and a first piece of data; and
a selector configured to output the first command/address signal and the first piece of data to the memory device based on detection of the entry to the self-refresh mode, and output a second command/address signal and a second piece of data provided from the host to the memory device, based on detection of the exit from the self-refresh mode.