| CPC G11C 11/406 (2013.01) [G11C 7/12 (2013.01); G11C 11/4085 (2013.01); G11C 11/4087 (2013.01); G11C 11/4091 (2013.01); G11C 11/40611 (2013.01); G11C 11/40622 (2013.01); G11C 7/1078 (2013.01); G11C 8/10 (2013.01)] | 17 Claims |
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1. A memory device comprising:
a memory cell array having a plurality of memory cells disposed in a plurality of rows and a plurality of columns and connected to a plurality of wordlines and a plurality of bitlines;
a row decoder configured to select a wordline, among the plurality of wordlines, in response to a row address;
a column decoder configured to select corresponding bitlines, among the plurality of bitlines, in response to a column address;
a sense amplification circuit having a plurality of amplifiers connected to the selected corresponding bitlines;
a row hammer detector configured to receive the row address, and to output a refresh row address generated from the row address when the number of accesses to a row corresponding to the row address is a multiple of a predetermined value; and
a refresh controller configured to perform a refresh operation on a row corresponding to the refresh row address,
wherein the row corresponding to the refresh row address is disposed adjacent to the row corresponding to the row address, and
wherein, the memory device is configured such that when the row hammer detector has no space to store die row address, the row hammer detector adjusts the number of row accesses to manage a missed row address not stored in the row hammer detector.
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