US 11,670,350 B2
Data input buffer and semiconductor apparatus including the same
Soon Sung An, Icheon-si (KR); and Kwan Su Shon, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Sep. 13, 2021, as Appl. No. 17/473,240.
Claims priority of application No. 10-2021-0050574 (KR), filed on Apr. 19, 2021.
Prior Publication US 2022/0335989 A1, Oct. 20, 2022
Int. Cl. G11C 7/10 (2006.01); H03K 19/00 (2006.01)
CPC G11C 7/1048 (2013.01) [G11C 7/1057 (2013.01); G11C 7/1084 (2013.01); H03K 19/0005 (2013.01); G11C 2207/2254 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A data input buffer comprising:
a plurality of buffer units configured to receive a first impedance calibration code and a second impedance calibration code,
wherein each of the plurality of buffer units outputs an offset detected with a first input terminal and a second input terminal thereof short-circuited, as write data, and
wherein a buffer unit corresponding to a current value of the first impedance calibration code among the plurality of buffer units is configured to correct the offset according to the second impedance calibration code.