CPC G11C 7/1048 (2013.01) [G11C 7/1057 (2013.01); G11C 7/1084 (2013.01); H03K 19/0005 (2013.01); G11C 2207/2254 (2013.01)] | 20 Claims |
1. A data input buffer comprising:
a plurality of buffer units configured to receive a first impedance calibration code and a second impedance calibration code,
wherein each of the plurality of buffer units outputs an offset detected with a first input terminal and a second input terminal thereof short-circuited, as write data, and
wherein a buffer unit corresponding to a current value of the first impedance calibration code among the plurality of buffer units is configured to correct the offset according to the second impedance calibration code.
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