CPC G11C 7/1048 (2013.01) [G11C 7/106 (2013.01); G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01)] | 9 Claims |
1. A semiconductor device comprising:
a write path control block including a first power gating circuit coupled to a supply terminal of a first voltage and a second power gating circuit coupled to a supply terminal of a second voltage, and a first logic circuit coupled to a supply terminal of a third voltage and a supply terminal of a fourth voltage, the write path control block suitable for generating a write control signal using the first and second voltages in a write mode;
a write driving block including only a third power gating circuit having a header-only power gating structure coupled to the supply terminal of the first voltage, and a second logic circuit coupled to any one of the supply terminal of the third voltage and the supply terminal of the fourth voltage, the write driving block suitable for transmitting a data signal to a data input/output line using the first and second voltages based on the write control signal; and
a memory block, coupled to the data input/output line, suitable for writing the data signal.
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