US 11,670,347 B2
Semiconductor memory device with power gating circuit for data input/output control block and data input/output block and semiconductor system including the same
Woongrae Kim, Gyeonggi-do (KR); Yoo-Jong Lee, Gyeonggi-do (KR); and A-Ram Rim, Seoul (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Feb. 12, 2021, as Appl. No. 17/174,527.
Application 17/174,527 is a division of application No. 16/232,205, filed on Dec. 26, 2018, granted, now 10,943,626.
Claims priority of provisional application 62/610,452, filed on Dec. 26, 2017.
Prior Publication US 2021/0166739 A1, Jun. 3, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/10 (2006.01)
CPC G11C 7/1048 (2013.01) [G11C 7/106 (2013.01); G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a write path control block including a first power gating circuit coupled to a supply terminal of a first voltage and a second power gating circuit coupled to a supply terminal of a second voltage, and a first logic circuit coupled to a supply terminal of a third voltage and a supply terminal of a fourth voltage, the write path control block suitable for generating a write control signal using the first and second voltages in a write mode;
a write driving block including only a third power gating circuit having a header-only power gating structure coupled to the supply terminal of the first voltage, and a second logic circuit coupled to any one of the supply terminal of the third voltage and the supply terminal of the fourth voltage, the write driving block suitable for transmitting a data signal to a data input/output line using the first and second voltages based on the write control signal; and
a memory block, coupled to the data input/output line, suitable for writing the data signal.