CPC G11C 7/1018 (2013.01) [G11C 7/1096 (2013.01); G11C 7/222 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/3454 (2013.01)] | 20 Claims |
1. A memory, comprising:
an array of memory cells comprising a plurality of strings of series-connected memory cells;
a plurality of access lines, wherein each access line of the plurality of access lines is connected to a respective plurality of memory cells of the array of memory cells; and
a controller for access of the array of memory cells, wherein the controller is configured to cause the memory to:
apply a respective programming pulse having a first target voltage level and a first pulse width to each access line of a first subset of access lines of the plurality of access lines during programming of the respective pluralities of memory cells for each access line of the plurality of access lines, wherein each access line of the first subset of access lines is connected to a respective memory cell of a string of series-connected memory cells of the plurality of strings of series-connected memory cells; and
apply a respective programming pulse having the first target voltage level and a second pulse width longer than the first pulse width to each access line of a second subset of access lines of the plurality of access lines during the programming of the respective pluralities of memory cells for each access line of the plurality of access lines, wherein each access line of the second subset of access lines is connected to a respective memory cell of the string of series-connected memory cells, and wherein each access line of the first subset of access lines is nearer a particular end of the string of series-connected memory cells than each access line of the second subset of access lines.
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