US 11,670,215 B2
Display device including a data driver performing clock training, and method of operating the display device
Soo Yeon Kim, Namyangju-si (KR); Tae Gon Im, Gwangmyeong-si (KR); and Hee-Jeong Seo, Hwaseong-si (KR)
Assigned to Samsung Display Co., Ltd., Gyeonggi-Do Yongin-Si (KR)
Filed by Samsung Display Co., Ltd., Yongin-Si (KR)
Filed on Sep. 3, 2020, as Appl. No. 17/11,967.
Claims priority of application No. 10-2020-0028617 (KR), filed on Mar. 6, 2020.
Prior Publication US 2021/0280125 A1, Sep. 9, 2021
Int. Cl. G09G 3/20 (2006.01)
CPC G09G 3/2092 (2013.01) [G09G 2310/0275 (2013.01); G09G 2310/061 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A display device comprising:
a display panel including a plurality of pixels;
a controller configured to provide a clock-embedded data signal, the clock-embedded data signal including image data in an active period and including a training pattern in a blank period;
a data driver configured to receive the clock-embedded data signal, to recover the image data based on an internal clock signal in the active period, to provide data voltages corresponding to the image data to the plurality of pixels in the active period, and to perform a training operation for the internal clock signal using the training pattern,
wherein the training pattern in the blank period includes a first training clock signal modulated with a first modulation period during a first time, and includes a second training clock signal modulated with a second modulation period different from the first modulation period after the first time such that the first and second training clock signals having the different first and second modulation periods are sequentially transferred within the same blank period,
wherein the first training clock signal is modulated with the first modulation period corresponding to three times of a clock period of the internal clock signal such that the first training clock signal periodically has a high period of about four unit intervals, a low period of about five unit intervals, a high period of about seven unit intervals, a low period of about five unit intervals, a high period of about four unit intervals and a low period of about five unit intervals, and
wherein the second training clock signal is modulated with the second modulation period corresponding to two times of the clock period of the internal clock signal such that the second training clock signal periodically has a high period of about six unit intervals, a low period of about four unit intervals, a high period of about four unit intervals and a low period of about six unit intervals.