US 11,670,044 B2
Fragment compression for coarse pixel shading
Prasoonkumar Surti, Folsom, CA (US); Abhishek R. Appu, El Dorado Hills, CA (US); Subhajit Dasgupta, Bangalore (IN); Srivallaba Mysore, Folsom, CA (US); Michael J. Norris, Folsom, CA (US); Vasanth Ranganathan, El Dorado Hills, CA (US); and Joydeep Ray, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 18, 2022, as Appl. No. 17/723,328.
Application 17/723,328 is a continuation of application No. 16/922,094, filed on Jul. 7, 2020, granted, now 11,315,311.
Application 16/922,094 is a continuation of application No. 15/493,214, filed on Apr. 21, 2017, granted, now 10,706,616, issued on Jul. 7, 2020.
Prior Publication US 2022/0327772 A1, Oct. 13, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06T 15/80 (2011.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01); G06T 15/00 (2011.01)
CPC G06T 15/80 (2013.01) [G06T 1/20 (2013.01); G06T 1/60 (2013.01); G06T 15/005 (2013.01); G06T 2210/52 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A graphics processor comprising:
a processing cluster including a plurality of processing elements configured to perform coarse pixel shading and output shaded coarse pixels for processing by a post-shader pixel pipeline;
a render cache to store coarse pixel data processed by and output from a pixel processing unit of the post-shader pixel pipeline; and
a graphics processor cache to store coarse pixel data evicted from the render cache as a coarse pixel.