US 11,669,773 B2
Electronic devices generating verification vector for verifying semiconductor circuit and methods of operating the same
Seungju Kim, Suwon-si (KR); Hyojin Choi, Seoul (KR); In Huh, Seoul (KR); Jeonghoon Ko, Hwaseong-si (KR); Changwook Jeong, Busan (KR); Younsik Park, Hwaseong-si (KR); and Joonwan Chai, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd.
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jun. 29, 2020, as Appl. No. 16/915,786.
Claims priority of application No. 10-2019-0130822 (KR), filed on Oct. 21, 2019.
Prior Publication US 2021/0117193 A1, Apr. 22, 2021
Int. Cl. G06N 20/00 (2019.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 30/3308 (2020.01); G06F 18/214 (2023.01)
CPC G06N 20/00 (2019.01) [G06F 9/30036 (2013.01); G06F 9/3879 (2013.01); G06F 18/214 (2023.01); G06F 30/3308 (2020.01)] 20 Claims
OG exemplary drawing
 
1. An electronic device configured to generate a verification vector for verifying a semiconductor circuit including a first circuit block and a second circuit block, the electronic device comprising:
a duplicate command eliminator configured to receive a first input vector including a plurality of commands and to provide a first converted vector, in which ones of the plurality of commands that generate the same state transition are changed into idle commands, based on a state transition of the first circuit block obtained by performing a simulation operation on the first input vector;
a reduced vector generator configured to provide a first reduced vector in which a number of repetitions of the idle commands included in the first converted vector is reduced; and
a verification vector generator configured to output the first reduced vector selected based on a coverage and a number of the idle commands among a plurality of first reduced vectors, as a first verification vector,
wherein the verification vector generator is configured to train an estimation model for estimating the first verification vector based on the number of the idle commands included in the first reduced vector and the coverage of the first reduced vector and output the first verification vector based on the trained estimation model.