US 11,669,721 B2
Tunable CMOS circuit, template matching module, neural spike recording system, and fuzzy logic gate
Alexantrou Serb, Southampton (GB); and Themistoklis Prodromakis, Southampton (GB)
Assigned to UNIVERSITY OF SOUTHAMPTON, Southampton (GB)
Appl. No. 16/617,377
Filed by UNIVERSITY OF SOUTHAMPTON, Southampton (GB)
PCT Filed May 29, 2018, PCT No. PCT/GB2018/051452
§ 371(c)(1), (2) Date Nov. 26, 2019,
PCT Pub. No. WO2018/215804, PCT Pub. Date Nov. 29, 2018.
Claims priority of application No. 1708512 (GB), filed on May 26, 2017.
Prior Publication US 2021/0004669 A1, Jan. 7, 2021
Int. Cl. G06N 3/065 (2023.01); G06N 3/049 (2023.01); G11C 11/413 (2006.01); G11C 11/54 (2006.01); H03K 19/20 (2006.01)
CPC G06N 3/065 (2023.01) [G06N 3/049 (2013.01); G11C 11/413 (2013.01); G11C 11/54 (2013.01); H03K 19/20 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A tunable complementary metal oxide semiconductor (CMOS) circuit comprising
a CMOS element configured to receive an analogue input signal, and
a tunable load connected to the CMOS element and configured to set a switch point of the CMOS element,
wherein the CMOS element is configured to output an output current, the output current being largest when the analogue input signal is equal to the switch point.