US 11,669,667 B2
Automatic test pattern generation (ATPG) for parametric faults
Peilin Jiang, Santa Clara, CA (US); Mayukh Bhattacharya, Palo Alto, CA (US); and Chih Ping Antony Fan, Saratoga, CA (US)
Assigned to Synopsys, Inc., Mountain View, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Feb. 19, 2021, as Appl. No. 17/180,013.
Claims priority of provisional application 62/979,725, filed on Feb. 21, 2020.
Prior Publication US 2021/0264087 A1, Aug. 26, 2021
Int. Cl. G06F 30/367 (2020.01); G06N 7/00 (2023.01); G06F 111/04 (2020.01); G06F 111/10 (2020.01); G06F 119/12 (2020.01)
CPC G06F 30/367 (2020.01) [G06N 7/005 (2013.01); G06F 2111/04 (2020.01); G06F 2111/10 (2020.01); G06F 2119/12 (2020.01)] 18 Claims
OG exemplary drawing
 
1. A method, comprising:
determining a set of measurements for a metric of an integrated circuit (IC) design by simulating the IC design over a set of random samples of random variables;
determining a first set of measurement margins based on the set of measurements, wherein each measurement margin corresponds to a difference between a measurement and a threshold;
constructing a Gaussian process (GP) model based on the first set of measurement margins, wherein the GP model predicts a second set of measurement margins that would be generated by simulating the IC design; and
determining, by a processor, a set of failure events for the IC design using the GP model, wherein each failure event corresponds to a set of values of the random variables that is expected to cause the metric of the IC design to violate the threshold.