CPC G06F 30/327 (2020.01) [G06F 30/343 (2020.01); H03K 19/1731 (2013.01); H03K 19/17728 (2013.01); G06F 30/323 (2020.01); G06F 30/337 (2020.01); G06F 30/34 (2020.01); G06F 30/373 (2020.01); G06F 30/398 (2020.01)] | 20 Claims |
1. A method comprising:
accessing a description of an application-specific integrated circuit (ASIC), the description comprising a logic network that implements a functionality of the ASIC;
mapping, by a processor, the logic network to a network of lookup tables (LUTs), wherein a LUT with k inputs can represent any function on k variables and the mapping is based at least in part on estimated areas of the LUTs; and
reducing the network of LUTs to a gate-level netlist of standard cells.
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