US 11,669,665 B1
Application-specific integrated circuit (ASIC) synthesis based on lookup table (LUT) mapping and optimization
Luca Gaetano Amaru, Santa Clara, CA (US); Vinicius Neves Possani, Sunnyvale, CA (US); Eleonora Testa, Vaud (CH); Felipe dos Santos Marranghello, Sunnyvale, CA (US); Christopher Casares, Sunnyvale, CA (US); Jiong Luo, Mountain View, CA (US); and Patrick Vuillod, Mountain View, CA (US)
Assigned to Synopsys, Inc., Mountain View, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Nov. 16, 2021, as Appl. No. 17/527,911.
Claims priority of provisional application 63/114,245, filed on Nov. 16, 2020.
Int. Cl. G06F 30/327 (2020.01); G06F 30/343 (2020.01); G06F 30/323 (2020.01); G06F 30/337 (2020.01); G06F 30/34 (2020.01); G06F 30/373 (2020.01); G06F 30/398 (2020.01); H03K 19/17 (2006.01); H03K 19/173 (2006.01); H03K 19/17728 (2020.01)
CPC G06F 30/327 (2020.01) [G06F 30/343 (2020.01); H03K 19/1731 (2013.01); H03K 19/17728 (2013.01); G06F 30/323 (2020.01); G06F 30/337 (2020.01); G06F 30/34 (2020.01); G06F 30/373 (2020.01); G06F 30/398 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
accessing a description of an application-specific integrated circuit (ASIC), the description comprising a logic network that implements a functionality of the ASIC;
mapping, by a processor, the logic network to a network of lookup tables (LUTs), wherein a LUT with k inputs can represent any function on k variables and the mapping is based at least in part on estimated areas of the LUTs; and
reducing the network of LUTs to a gate-level netlist of standard cells.