US 11,669,489 B2
Sparse systolic array design
Swagath Venkataramani, White Plains, NY (US); Sanchari Sen, West Lafayette, IN (US); Vijayalakshmi Srinivasan, New York, NY (US); Ankur Agrawal, Chappaqua, NY (US); Sunil K Shukla, Scarsdale, NY (US); Bruce Fleischer, Bedford Hills, NY (US); and Kailash Gopalakrishnan, New York, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Sep. 30, 2021, as Appl. No. 17/490,830.
Prior Publication US 2023/0109301 A1, Apr. 6, 2023
Int. Cl. G06F 15/80 (2006.01); G06F 9/30 (2018.01); G06F 7/50 (2006.01); G06F 7/544 (2006.01); G06F 7/523 (2006.01)
CPC G06F 15/8046 (2013.01) [G06F 7/50 (2013.01); G06F 7/523 (2013.01); G06F 7/5443 (2013.01); G06F 9/3001 (2013.01); G06F 9/30069 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a first row of processing elements;
a memory; and
a skip module, the skip module configured to:
receive a sequence of operands from the memory, the sequence including at least a first operand and a second operand;
generate a first operand vector based on an identification that the first operand is a nonzero operand;
skip the second operand based on an identification that the second operand is a zero-value operand; and
send the first operand vector to each processing element included in the first row of processing elements.