US 11,669,464 B1
Multi-addressing mode for DMA and non-sequential read and write patterns
Goran Hk Bilski, Molndal (SE); Baris Ozgul, Dublin (IE); David Clarke, Dublin (IE); Juan J. Noguera Serra, San Jose, CA (US); Jan Langer, Chemnitz (DE); Zachary Dickman, Dublin (IE); Sneha Bhalchandra Date, San Jose, CA (US); and Tim Tuan, San Jose, CA (US)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by XILINX, INC., San Jose, CA (US)
Filed on Apr. 24, 2020, as Appl. No. 16/858,417.
Int. Cl. G06F 12/1081 (2016.01); G06F 12/06 (2006.01); G06F 9/52 (2006.01); G06F 15/78 (2006.01); G06F 12/02 (2006.01)
CPC G06F 12/1081 (2013.01) [G06F 9/524 (2013.01); G06F 12/0246 (2013.01); G06F 12/0607 (2013.01); G06F 15/7807 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC), comprising:
a switch;
a direct memory access (DMA) engine comprising multiple reconfigurable buffer descriptors configured with respective address generation parameters; and
a memory;
wherein the DMA engine is configured to:
receive data from the switch,
select a first one of the buffer descriptors for a first DMA write request based on a first instruction received by the DMA engine, and
write the data to the memory in a first non-sequential write pattern based on the address generation parameters of the first buffer descriptor.