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1. A processor comprising: one or more cores, each comprising cache; a cache home agent (CHA) coupled to the cache; and a near memory controller coupled to the CHA, to near memory, and to a far memory controller, wherein the near memory controller is to: receive a first memory read operation from the CHA directed at a memory address; detect a miss for the memory address at the near memory; issue, in response to detection of the miss, a second memory read operation to the far memory controller to retrieve a cache line, comprising first data, from the memory address of far memory; receive the cache line from the far memory controller in response to completion of the second memory read operation; and in response to the cache line being retrieved from the far memory, send the cache line to the CHA with a change to a directory state of the cache line at the CHA, the changed directory state to cause the CHA to snoop remote sockets to maintain data coherence for the cache line, and write the cache line to the near memory with a set of metadata bits indicating that the cache line is clean and directory bits in the cache line are dirty, wherein based on the set of metadata bits, the cache line is not written to the far memory in response to the cache line being selected to be evicted from the near memory, wherein the near memory maintains the data coherence using directory state in an absence of directory state in the far memory.
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