US 11,669,448 B2
Transmitters for generating multi-level signals and memory system including the same
Hyungmin Jin, Seoul (KR); Jindo Byun, Suwon-si (KR); Younghoon Son, Yongin-si (KR); Youngdon Choi, Seoul (KR); and Junghwan Choi, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on May 14, 2021, as Appl. No. 17/320,460.
Claims priority of application No. 10-2020-0117104 (KR), filed on Sep. 11, 2020.
Prior Publication US 2022/0075725 A1, Mar. 10, 2022
Int. Cl. G06F 12/0802 (2016.01); G11C 7/10 (2006.01); G11C 8/06 (2006.01); H03K 19/00 (2006.01); H03K 19/0185 (2006.01)
CPC G06F 12/0802 (2013.01) [G11C 7/1048 (2013.01); G11C 8/06 (2013.01); H03K 19/0027 (2013.01); H03K 19/018521 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A multi-level signal transmitter, comprising:
a first voltage selection circuit configured to select one amongst a first plurality of driving voltages having different voltage levels, in response to input data including at least two bits of data therein; and
a driver circuit configured to generate an output data signal in response to the selected one of the first plurality of driving voltages, which is provided as a body bias voltage to at least one transistor within the driver circuit, said driver circuit comprising:
a first totem pole arrangement of a NMOS pull-up transistor and a PMOS pull-down transistor; and
a second totem pole arrangement of a PMOS pull-up transistor and an NMOS pull-down transistor.