CPC G06F 12/0802 (2013.01) [G11C 7/1048 (2013.01); G11C 8/06 (2013.01); H03K 19/0027 (2013.01); H03K 19/018521 (2013.01)] | 8 Claims |
1. A multi-level signal transmitter, comprising:
a first voltage selection circuit configured to select one amongst a first plurality of driving voltages having different voltage levels, in response to input data including at least two bits of data therein; and
a driver circuit configured to generate an output data signal in response to the selected one of the first plurality of driving voltages, which is provided as a body bias voltage to at least one transistor within the driver circuit, said driver circuit comprising:
a first totem pole arrangement of a NMOS pull-up transistor and a PMOS pull-down transistor; and
a second totem pole arrangement of a PMOS pull-up transistor and an NMOS pull-down transistor.
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