US 11,669,395 B2
Memory system including field programmable gate array (FPGA) and method of operating same
Dong-Min Shin, Seoul (KR); and Hong-Rak Son, Anyang-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Oct. 12, 2021, as Appl. No. 17/499,499.
Application 17/499,499 is a continuation of application No. 16/547,425, filed on Aug. 21, 2019, granted, now 11,169,874.
Claims priority of application No. 10-2018-0156277 (KR), filed on Dec. 6, 2018.
Prior Publication US 2022/0035703 A1, Feb. 3, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); H03M 13/09 (2006.01); H03M 13/11 (2006.01); G06F 7/58 (2006.01); G11C 11/409 (2006.01); G11C 29/52 (2006.01); G06F 13/16 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 7/58 (2013.01); G06F 13/1668 (2013.01); G11C 11/409 (2013.01); G11C 29/52 (2013.01); H03M 13/095 (2013.01); H03M 13/1105 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system comprising:
a memory device; and
a memory controller comprising a first interface, a second interface, a first data processor, and a second data processor,
wherein the first data processor is configured to perform a first data processing on read data retrieved via the first interface from the memory device and output first-processed read data via one of the second interface and the second data processor,
wherein the second data processor is configured to perform a second data processing on the first processed read data and output second-processed read data to an external host via the second interface, and
wherein the second data processor comprises a second error correction code (ECC) engine configured to perform a second ECC decoding on the first-processed read data received from the first data processor to provide the second-processed read data.