CPC G06F 11/1068 (2013.01) [G06F 7/58 (2013.01); G06F 13/1668 (2013.01); G11C 11/409 (2013.01); G11C 29/52 (2013.01); H03M 13/095 (2013.01); H03M 13/1105 (2013.01)] | 20 Claims |
1. A memory system comprising:
a memory device; and
a memory controller comprising a first interface, a second interface, a first data processor, and a second data processor,
wherein the first data processor is configured to perform a first data processing on read data retrieved via the first interface from the memory device and output first-processed read data via one of the second interface and the second data processor,
wherein the second data processor is configured to perform a second data processing on the first processed read data and output second-processed read data to an external host via the second interface, and
wherein the second data processor comprises a second error correction code (ECC) engine configured to perform a second ECC decoding on the first-processed read data received from the first data processor to provide the second-processed read data.
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