US 11,669,314 B2
Method and system to enable print functionality in high-level synthesis (HLS) design platforms
Nupur Sumeet, Thane West (IN); and Manoj Nambiar, Thane West (IN)
Assigned to TATA CONSULTANCY SERVICES LIMITED, Mumbai (IN)
Filed by Tata Consultancy Services Limited, Mumbai (IN)
Filed on Dec. 27, 2021, as Appl. No. 17/562,378.
Claims priority of application No. 202121014186 (IN), filed on Mar. 30, 2021.
Prior Publication US 2022/0350580 A1, Nov. 3, 2022
Int. Cl. G06F 8/51 (2018.01); G06F 8/10 (2018.01); G06F 8/30 (2018.01); G06F 8/41 (2018.01); G06F 30/327 (2020.01)
CPC G06F 8/51 (2013.01) [G06F 8/10 (2013.01); G06F 8/315 (2013.01); G06F 8/458 (2013.01); G06F 30/327 (2020.01)] 13 Claims
OG exemplary drawing
 
1. A processor-implemented method comprising:
receiving a source code associated with an IT application at a High-Level Synthesis (HLS) platform, via a one or more hardware processors, wherein the source code comprises at least a print statement with a set of print variables to be printed, the source code is associated with a source code operation frequency and the IT application utilizes a Field Programmable Gate Array (FPGA) as a processing platform that is associated with a peripheral component interconnect express (PCIe) bandwidth threshold limit;
receiving a plurality of low level integration inputs at the HLS platform, via the one or more hardware processors, wherein the low level integration inputs are associated with the FPGA and comprises a cycle counter, an application counter and a stream ID generator;
updating the source code, via the one or more hardware processors, to obtain a print version of the source code by including a set of HLS print statements;
pre-processing the print version of the source code to obtain a synthesizable source code, via the one or more hardware processors, using a source-to-source transformations based on a code generation script;
synthesizing the synthesizable source code to obtain an HLS_IP (HLS_Intellectual Property), via the one or more hardware processors, based on the source code operation frequency;
determining if the HLS_IP is within the PCIe bandwidth threshold limit, via the one or more hardware processors, based on the determination creating a plurality of print records in HLS_IP using the plurality of low level integration input, wherein a print record is created for every print variable from the set of print variables;
connecting the plurality of print records to a plurality of First in First out (FIFO) units, via the one or more hardware processors, wherein each print record from the plurality of print records is connected to a FIFO unit from amongst the plurality of First in First out (FIFO) units;
combining the plurality of print records to obtain a valid sequential print record, via the one or more hardware processors, wherein the combining includes scanning the plurality of print records using a stream combining scheme based on round robin technique;
synthesizing a Hardware Development Language (HDL) design using the HLS_IP, via the one or more hardware processors, the plurality of print records and the valid sequential print record and creating an executable bitstream of the HDL design;
sharing the executable bitstream with an FPGA, via the one or more hardware processors, for processing;
receiving the processed sequential print records from the FPGA over a PCIe at a host, wherein the processed sequential print records is in a binary format; and
converting the processed sequential print records to a human interpretable data in the host, via the one or more hardware processors, using a formatter technique and printing the human interpretable data.