US 11,669,304 B2
Arithmetic device and arithmetic circuit for performing multiplication and division
Mikio Shiraishi, Yokohama (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Jun. 18, 2021, as Appl. No. 17/351,887.
Claims priority of application No. JP2021-018196 (JP), filed on Feb. 8, 2021.
Prior Publication US 2022/0253286 A1, Aug. 11, 2022
Int. Cl. G06F 7/57 (2006.01); G06F 7/52 (2006.01)
CPC G06F 7/57 (2013.01) [G06F 7/52 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An arithmetic device including:
a first input terminal configured to receive a first signal that transmits an input bit string;
a second input terminal configured to receive a second signal that includes first to eighth control signals;
an output terminal configured to output a signal indicating a product of a value indicated by the first signal and a value indicated by the second signal;
a first logical shifter configured to output a first bit string obtained by shifting left a sequence of bits of the input bit string by one bit;
a second logical shifter configured to output a second bit string obtained by shifting left a sequence of bits of the first bit string by one bit;
a third logical shifter configured to output a third bit string obtained by shifting left a sequence of bits of the second bit string by one bit;
a first AND gate configured to output a fourth bit string that is an arithmetic result of a logical product of values of the input bit string and the first control signal;
a second AND gate configured to output a fifth bit string that is an arithmetic result of a logical product of values of the first bit string and the second control signal;
a first multiplexer configured to output, based on the third control signal, a sixth bit string that is either the second bit string or the third bit string;
a third AND gate configured to output a seventh bit string that is an arithmetic result of a logical product of values of the sixth bit string and the fourth control signal;
a first adder configured to output an eighth bit string that is a sum of the seventh bit string and the fifth bit string;
a fourth logical shifter configured to output a ninth bit string obtained by shifting left a sequence of bits of the eighth bit string by one bit;
a second multiplexer configured to output, based on the fifth control signal, a tenth bit string that is either the eighth bit string or the ninth bit string;
a second adder configured to output an eleventh bit string that is a sum of the fourth bit string and the tenth bit string;
a first arithmetic shifter configured to output a twelfth bit string obtained by shifting right a sequence of bits of the eleventh bit string by five bits while maintaining a sign;
a second arithmetic shifter configured to output a thirteenth bit string obtained by shifting right a sequence of bits of the twelfth bit string by one bit while maintaining a sign;
a third arithmetic shifter configured to output a fourteenth bit string obtained by shifting right a sequence of bits of the thirteenth bit string by one bit while maintaining a sign;
a third multiplexer configured to output, based on the sixth control signal, a fifteenth bit string that is either the eleventh bit string or the twelfth bit string;
a fourth multiplexer configured to output, based on the seventh control signal, a sixteenth bit string that is either the thirteenth bit string or the fourteenth bit string; and
a fifth multiplexer configured to output, as the signal indicating the product, an output signal that transmits either the fifteenth bit string or the sixteenth bit string based on the eighth control signal.