US 11,668,749 B2
Method for eliminating fake faults in gate-level simulation
Chia-Cheng Pai, Taipei (TW)
Assigned to SILICON MOTION, INC., Jhubei (TW)
Filed by Silicon Motion, Inc., Jhubei (TW)
Filed on Aug. 26, 2020, as Appl. No. 17/2,870.
Prior Publication US 2022/0065931 A1, Mar. 3, 2022
Int. Cl. G01R 27/28 (2006.01); G01R 31/317 (2006.01); G01R 31/3193 (2006.01)
CPC G01R 31/31725 (2013.01) [G01R 31/31937 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method for adjusting propagation delay of each path in an integrated circuit, comprising:
determining, in a worst-based mode, whether a propagation delay of a selected path exceeds a timing requirement;
determining, in a path-based mode, whether the propagation delay of the selected path exceeds the timing requirement; and
when the selected path does not exceed the timing requirement in the path-based mode, lowering a cell delay in the worst-based mode of each cell in the selected path, wherein the step of lowering the delay in the worst-based mode of each cell in the selected path further comprises:
lowering a maximal cell delay in the worst-based mode of each cell in the selected path.