US 11,668,748 B2
Addressable test chip
Fan Lan, Hangzhou (CN); Weiwei Pan, Hangzhou (CN); Shenzhi Yang, Hangzhou (CN); and Yongjun Zheng, Hangzhou (CN)
Assigned to SEMITRONIX CORPORATION, Hangzhou (CN)
Filed by SEMITRONIX CORPORATION, Hangzhou (CN)
Filed on Jan. 25, 2022, as Appl. No. 17/648,935.
Application 17/648,935 is a continuation of application No. 16/940,372, filed on Jul. 27, 2020, granted, now 11,243,251.
Application 16/940,372 is a continuation of application No. 16/377,422, filed on Apr. 8, 2019, granted, now 10,725,101, issued on Jul. 28, 2020.
Application 16/377,422 is a continuation of application No. 15/859,306, filed on Dec. 29, 2017, granted, now 10,254,339, issued on Apr. 9, 2019.
Claims priority of application No. 201611260100.3 (CN), filed on Dec. 30, 2016; application No. 201822250453.6 (CN), filed on Dec. 29, 2018; application No. 201822254087.1 (CN), filed on Dec. 29, 2018; application No. 201920376170.8 (CN), filed on Mar. 22, 2019; application No. 202010687645.2 (CN), filed on Jul. 16, 2020; application No. 202021406599.6 (CN), filed on Jul. 16, 2020; and application No. 202111501691.X (CN), filed on Dec. 9, 2021.
Prior Publication US 2022/0146573 A1, May 12, 2022
Int. Cl. G01R 31/317 (2006.01); G01R 31/28 (2006.01)
CPC G01R 31/31722 (2013.01) [G01R 31/2882 (2013.01); G01R 31/2886 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An addressable test chip comprising:
a plurality of test pads;
a plurality of devices under test (DUTs); and
at least one peripheral circuit(s);
wherein:
the DUTs are divided into at least one device array(s);
the peripheral circuit is configured to select several DUTs among the device array to be test through the on-state or off-state of the peripheral circuit units;
the peripheral circuit is designed according to the DUTs in the edge row or/and edge column of the device array, comprising: in the peripheral circuit area, configure the corresponding peripheral circuit unit for each DUT in the edge row or/and edge column of the device array, and place the peripheral circuit units, connect the DUTs of the device array and the corresponding peripheral circuit units through a wiring to form a peripheral circuit;
the peripheral circuit is designed according to the DUTs in the edge row or/and edge column of the device array, further comprising:
the row direction of an edge row or the column direction of the edge column is defined as X direction, and the peripheral circuit units to be placed meet the conditions comprising:
the first condition: the projection of the peripheral circuit unit and the projection of its corresponding DUT overlap in the X direction;
the second condition: there is no overlap in the X direction of the projection of peripheral circuit units in the same row or column;
the third condition: the peripheral circuit unit are placed within the peripheral circuit area.