US 11,659,720 B2
Silicon over insulator two-transistor one-resistor in-series resistive memory cell
Lior Dagan, Tzafon (IL)
Assigned to WEEBIT NANO LTD., Hod Hasharon (IL)
Filed by Weebit Nano Ltd., Hod Hasharon (IL)
Filed on Jul. 12, 2021, as Appl. No. 17/373,102.
Claims priority of provisional application 63/052,111, filed on Jul. 15, 2020.
Prior Publication US 2022/0020815 A1, Jan. 20, 2022
Int. Cl. G11C 11/00 (2006.01); H01L 27/24 (2006.01); H01L 27/12 (2006.01); G11C 13/00 (2006.01)
CPC H01L 27/2436 (2013.01) [G11C 13/004 (2013.01); G11C 13/0069 (2013.01); H01L 27/1203 (2013.01); G11C 2213/74 (2013.01); G11C 2213/79 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A resistive random-access memory (ReRAM) cell comprising:
a silicon over insulator (SOI) substrate;
a first metal-oxide semiconductor field-effect transistor (MOSFET) formed on the SOI substrate having a drain port, a gate port, a source port, and a bulk port;
a second MOSFET formed on the SOI substrate having a drain port, a gate port, a source port, and a bulk port;
a resistive element formed on the SOI substrate having a first port and a second port;
a word line connected to the gate port of the first MOSFET;
an inverted word line of the word line connected to the gate port of the second MOSFET;
a bit line; and
an inverted bit line of the bit line;
wherein the first MOSFET, the second MOSFET, and the resistive element are connected in series between the bit line and the inverted bit line;
wherein upon applying a predefined potential at the bit line, the inverted bit line, the word line, the inverted word line, the bulk port of the first MOSFET, and the bulk port of the second MOSFET, a state of the ReRAM cell is determined.