US 11,659,710 B2
Memory structure and fabrication method thereof
Liang Han, Shanghai (CN); and Hai Ying Wang, Shanghai (CN)
Assigned to Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai (CN); and Semiconductor Manufacturing International (Beijing) Corporation, Beijing (CN)
Filed by Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai (CN); and Semiconductor Manufacturing International (Beijing) Corporation, Beijing (CN)
Filed on Sep. 22, 2020, as Appl. No. 17/28,673.
Claims priority of application No. 201910986115.5 (CN), filed on Oct. 16, 2019.
Prior Publication US 2021/0118893 A1, Apr. 22, 2021
Int. Cl. H01L 27/11521 (2017.01); H01L 27/11558 (2017.01); H01L 29/49 (2006.01)
CPC H01L 27/11521 (2013.01) [H01L 27/11558 (2013.01); H01L 29/4933 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A fabrication method of a memory structure, comprising: providing a substrate; forming a plurality of discrete memory gate structures on the substrate, wherein an isolation trench is between adjacent memory gate structures, and a memory gate structure of the plurality of discrete memory gate structures includes a floating gate layer and a control gate layer on the floating gate layer; forming an isolation layer in the isolation trench, wherein a top surface of the isolation layer is lower than a top surface of the control gate layer and higher than a bottom surface of the control gate layer; forming an opening on an exposed sidewall of the control gate layer, wherein a bottom of the opening is lower than or coplanar with the top surface of the isolation layer; and forming an initial metal silicide layer on an exposed surface of the control gate layer and the top surface of the isolation layer.