CPC H03K 17/102 (2013.01) [H02M 3/07 (2013.01); H02M 3/158 (2013.01); H03K 5/003 (2013.01); H03K 5/1534 (2013.01); H03K 17/687 (2013.01); H03K 19/017509 (2013.01); H03K 19/018507 (2013.01); H01L 21/84 (2013.01); H01L 21/86 (2013.01); H01L 27/088 (2013.01); H01L 27/0928 (2013.01); H01L 27/1203 (2013.01); H02M 1/08 (2013.01); H03K 2005/00293 (2013.01)] | 21 Claims |
1. A level shifter, comprising:
low voltage transistor devices configured to operate between a first voltage and a second voltage;
a first terminal configured to carry the first voltage;
a second terminal configured to carry the second voltage substantially corresponding to a sum of the first voltage and a low voltage;
input nodes configured to receive input timing control signals;
a parallel resistive-capacitive network coupled between the input nodes and the low voltage transistor devices; and
an output node configured to provide an output timing control signal, the output timing control signal being based on signal information of the input timing control signals through the parallel resistive-capacitive network.
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