US 11,658,622 B2
Power amplifier circuit
Satoshi Tanaka, Kyoto (JP); Kazuo Watanabe, Kyoto (JP); Yusuke Tanaka, Kyoto (JP); and Satoshi Arayashiki, Kyoto (JP)
Assigned to MURATA MANUFACTURING CO., LTD., Kyoto (JP)
Filed by Murata Manufacturing Co., Ltd., Kyoto (JP)
Filed on Mar. 22, 2021, as Appl. No. 17/207,879.
Application 17/207,879 is a continuation of application No. 16/549,057, filed on Aug. 23, 2019, granted, now 10,985,715.
Claims priority of application No. JP2018-165368 (JP), filed on Sep. 4, 2018.
Prior Publication US 2021/0234519 A1, Jul. 29, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H03F 1/22 (2006.01); H03F 3/217 (2006.01); H03F 1/56 (2006.01); H03F 1/02 (2006.01)
CPC H03F 3/217 (2013.01) [H03F 1/0205 (2013.01); H03F 1/565 (2013.01); H03F 3/2171 (2013.01); H03F 2200/171 (2013.01); H03F 2200/387 (2013.01); H03F 2200/451 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A power amplifier circuit comprising:
a lower transistor having a first terminal, a second terminal, and a third terminal, wherein a first power supply voltage is supplied to the first terminal, the second terminal is connected to ground, and an input signal is supplied to the third terminal;
a first capacitor;
an upper transistor having a first terminal, a second terminal, and a third terminal, wherein a second power supply voltage is supplied to the first terminal of the upper transistor, an amplified signal obtained by amplifying the input signal is output to an output terminal from the first terminal of the upper transistor, the second terminal of the upper transistor is connected to the first terminal of the lower transistor via the first capacitor, and a driving voltage is supplied to the third terminal of the upper transistor;
a first inductor that connects the second terminal of the upper transistor to ground; and
at least one termination circuit that short-circuits one of an even-order harmonic or an odd-order harmonic of the amplified signal to ground potential,
the at least one termination circuit being disposed so as to branch off from a node along a transmission path extending from the first terminal of the lower transistor to the output terminal through the first capacitor and the upper transistor.