CPC H01L 29/42344 (2013.01) [H01L 27/1157 (2013.01); H01L 27/11521 (2013.01); H01L 27/11524 (2013.01); H01L 27/11568 (2013.01); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H01L 29/42324 (2013.01); H01L 29/42348 (2013.01); H01L 29/518 (2013.01); H01L 29/6653 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01)] | 20 Claims |
1. An integrated chip, comprising:
a source/drain region arranged within a substrate;
a first select gate arranged over the substrate;
a first memory gate arranged over the substrate and separated from the source/drain region by the first select gate; and
an inter-gate dielectric structure arranged between the first memory gate and the first select gate, the inter-gate dielectric structure extending under the first memory gate, wherein a height of a part of the inter-gate dielectric structure that is laterally between the first select gate and the first memory gate is smaller than a height of the first select gate.
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