US 11,658,177 B2
Semiconductor device structures with a substrate biasing scheme
Anthony K. Stamper, Williston, VT (US); Michel J. Abou-Khalil, Essex Junction, VT (US); John J. Ellis-Monaghan, Grand Isle, VT (US); Randy Wolf, Essex Junction, VT (US); Alvin J. Joseph, Williston, VT (US); and Aaron Vallett, Jericho, VT (US)
Assigned to GlobalFoundries U.S. Inc., Santa Clara, CA (US)
Filed by GLOBALFOUNDRIES U.S. Inc., Santa Clara, CA (US)
Filed on Dec. 7, 2020, as Appl. No. 17/113,473.
Prior Publication US 2022/0181317 A1, Jun. 9, 2022
Int. Cl. H01L 27/02 (2006.01); H01L 29/06 (2006.01)
CPC H01L 27/0285 (2013.01) [H01L 27/0218 (2013.01); H01L 29/0619 (2013.01); H01L 29/0649 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A structure comprising:
a bulk semiconductor substrate including a device region;
a substrate contact coupled to a portion of the bulk semiconductor substrate in the device region, the substrate contact configured to be biased with a first negative bias voltage;
a field-effect transistor including a semiconductor body in the device region of the bulk semiconductor substrate, the semiconductor body electrically isolated from the portion of the bulk semiconductor substrate; and
an isolation layer positioned between the semiconductor body and the portion of the bulk semiconductor substrate, the isolation layer comprising a polycrystalline semiconductor material.