US 11,658,072 B2
Vertically stacked transistors in a fin
Aaron D. Lilak, Beaverton, OR (US); Sean T. Ma, Portland, OR (US); Justin R. Weber, Hillsboro, OR (US); Patrick Morrow, Portland, OR (US); and Rishabh Mehandru, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 26, 2021, as Appl. No. 17/385,688.
Application 17/385,688 is a division of application No. 16/475,032, granted, now 11,075,119, previously published as PCT/US2017/025004, filed on Mar. 30, 2017.
Prior Publication US 2021/0351078 A1, Nov. 11, 2021
Int. Cl. H01L 21/822 (2006.01); H01L 21/02 (2006.01); H01L 21/225 (2006.01); H01L 21/265 (2006.01); H01L 21/683 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/167 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01)
CPC H01L 21/8221 (2013.01) [H01L 21/0217 (2013.01); H01L 21/02178 (2013.01); H01L 21/2252 (2013.01); H01L 21/26533 (2013.01); H01L 21/6835 (2013.01); H01L 21/762 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 29/167 (2013.01); H01L 29/401 (2013.01); H01L 29/66545 (2013.01); H01L 2221/6835 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a fin on a substrate;
forming a dielectric layer comprising a fixed charge along a central region of the fin, the dielectric layer dividing the fin into a first section above the dielectric layer and a second section below the dielectric layer;
selectively doping the first section of the fin to form one or more first transistors on the first section of the fin; and
selectively doping the second section of the fin to form one or more second transistors on the second section of the fin.