US 11,658,064 B2
Interconnect structure with dielectric cap layer and etch stop layer stack
Chao-Chun Wang, Hsinchu (TW); and Jen Hung Wang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Mar. 23, 2021, as Appl. No. 17/210,015.
Claims priority of provisional application 63/084,812, filed on Sep. 29, 2020.
Prior Publication US 2022/0102203 A1, Mar. 31, 2022
Int. Cl. H01L 21/768 (2006.01); H01L 23/532 (2006.01)
CPC H01L 21/76831 (2013.01) [H01L 21/76832 (2013.01); H01L 21/76879 (2013.01); H01L 23/53238 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor device, the method comprising:
forming a first conductive feature in a first dielectric layer disposed over a substrate;
forming a metal cap layer over an upper surface of the first conductive feature distal from the substrate;
selectively forming a dielectric cap layer over an upper surface of the first dielectric layer and laterally adjacent to the metal cap layer, wherein the metal cap layer is exposed by the dielectric cap layer; and
forming an etch stop layer stack over the metal cap layer and the dielectric cap layer, wherein the etch stop layer stack comprises a plurality of etch stop layers.