US 11,658,032 B2
Semiconductor epitaxy bordering isolation structure
Wen-Chin Chen, Kaohsiung (TW); Cheng-Yi Wu, Taichung (TW); Yu-Hung Cheng, Tainan (TW); Ren-Hua Guo, Taichung (TW); Hsiang Liu, Hsinchu (TW); and Chin-Szu Lee, Taoyuan (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Mar. 18, 2021, as Appl. No. 17/205,715.
Application 16/043,286 is a division of application No. 15/475,826, filed on Mar. 31, 2017, granted, now 10,147,609, issued on Dec. 4, 2018.
Application 17/205,715 is a continuation of application No. 16/719,311, filed on Dec. 18, 2019, granted, now 10,957,540.
Application 16/719,311 is a continuation of application No. 16/043,286, filed on Jul. 24, 2018, granted, now 10,522,353, issued on Dec. 31, 2019.
Claims priority of provisional application 62/434,966, filed on Dec. 15, 2016.
Prior Publication US 2021/0210350 A1, Jul. 8, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/78 (2006.01); H01L 21/331 (2006.01); H01L 21/20 (2006.01); H01L 29/66 (2006.01); H01L 29/04 (2006.01); H01L 21/02 (2006.01); H01L 29/08 (2006.01); H01L 29/165 (2006.01); H01L 21/306 (2006.01)
CPC H01L 21/2022 (2013.01) [H01L 21/02002 (2013.01); H01L 21/0243 (2013.01); H01L 21/0245 (2013.01); H01L 21/0262 (2013.01); H01L 21/02381 (2013.01); H01L 21/02502 (2013.01); H01L 21/02516 (2013.01); H01L 21/02532 (2013.01); H01L 21/02579 (2013.01); H01L 21/02636 (2013.01); H01L 21/02639 (2013.01); H01L 29/045 (2013.01); H01L 29/0847 (2013.01); H01L 29/165 (2013.01); H01L 29/66287 (2013.01); H01L 29/66628 (2013.01); H01L 29/66636 (2013.01); H01L 29/7848 (2013.01); H01L 21/30608 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first gate structure disposed over a substrate;
an isolation structure at least partially embedded in the substrate;
a first source/drain feature associated with the first gate structure, the first source/drain feature including:
a first semiconductor layer disposed on the substrate;
a second semiconductor layer disposed on the first semiconductor layer and interfacing with the isolation structure; and
a third semiconductor layer disposed on the second semiconductor layer and interfacing with the isolation structure; and
an inter-layer dielectric (ILD) layer disposed over the isolation structure and the first gate structure, wherein the ILD layer interfaces with a sidewall of the isolation structure.