US 11,657,883 B2
Isolating problematic memory planes to avoid neighbor plan disturb
Ke Zhang, Shanghai (CN); Liang Li, Shanghai (CN); and Jiahui Yuan, Fremont, CA (US)
Assigned to Western Digital Technologies, Inc., San Jose, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Jul. 22, 2021, as Appl. No. 17/382,424.
Prior Publication US 2023/0023618 A1, Jan. 26, 2023
Int. Cl. G11C 16/34 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01); G11C 16/10 (2006.01)
CPC G11C 16/3445 (2013.01) [G11C 16/08 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a control circuit configured to connect to a word line in each plane of a plurality of planes, each word line is connected to a respective set of memory cells, to perform a program operation for the respective sets of memory cells, the control circuit is configured to:
apply one or more common program pulses to each word line in a multi-plane program mode;
determine that at least a first set of memory cells has completed programming when a first number of common program pulses have been applied;
in response to determining that at least the first set of memory cells has completed programming, set a trigger number according to the first number;
determine that one or more respective sets of memory cells have not completed programming when the trigger number of common program pulses have been applied; and
in response to the determining that the one or more respective sets of memory cells have not completed programming when the trigger number of common program pulses have been applied, apply program pulses to word lines of the one or more respective sets of memory cells which have not completed programming in a single-plane program mode, one respective set of memory cells at a time, until no more than a maximum allowable number of program pulses have been applied.