US 11,657,873 B2
Non-volatile static random access memory (nvSRAM) with multiple magnetic tunnel junction cells
Perng-Fei Yuh, Hsinchu (TW); Yih Wang, Hsinchu (TW); Ku-Feng Lin, New Taipei (TW); Jui-Che Tsai, Tainan (TW); Hiroki Noguchi, Hsinchu (TW); and Fu-An Wu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 23, 2021, as Appl. No. 17/409,341.
Application 17/409,341 is a continuation of application No. 16/732,219, filed on Dec. 31, 2019, granted, now 11,107,530.
Prior Publication US 2021/0383867 A1, Dec. 9, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 14/00 (2006.01); G11C 11/419 (2006.01); G11C 11/16 (2006.01)
CPC G11C 14/0081 (2013.01) [G11C 11/161 (2013.01); G11C 11/1659 (2013.01); G11C 11/1675 (2013.01); G11C 11/419 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a first static random access memory (SRAM) having a first port and a second port;
a first set of magnetic tunnel junction (MTJ) cells, each of the first set of MTJ cells and a corresponding one of a first set of pass transistors coupled to each other in series between a first select line and the second port of the first SRAM, wherein the first set of MTJ cells includes a first reference MTJ cell having two electrodes coupled to the first select line and a first reference line, respectively;
a second set of MTJ cells, each of the second set of MTJ cells and a corresponding one of a second set of pass transistors coupled to each other in series between a second select line and the first port of the first SRAM, wherein the second set of MTJ cells includes a second reference MTJ cell having two electrodes coupled to the second select line and a second reference line, respectively;
wherein the first set of MTJ cells each store a first bit independent of a second bit that the second set of MTJ cells each store.