US 11,657,869 B2
SRAM design with four-poly-pitch
Chih-Chuan Yang, Tainan (TW); Feng-Ming Chang, Zhubei (TW); Kuo-Hsiu Hsu, Zhongli (TW); and Ping-Wei Wang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Nov. 17, 2021, as Appl. No. 17/528,929.
Application 17/528,929 is a continuation of application No. 16/926,249, filed on Jul. 10, 2020, granted, now 11,205,474.
Prior Publication US 2022/0076740 A1, Mar. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/412 (2006.01); H01L 27/11 (2006.01)
CPC G11C 11/412 (2013.01) [H01L 27/1104 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory cell, comprising:
a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, and a fifth gate structure that each extend along a first lateral direction, wherein the first and second gate structures are aligned with each other, with the fourth and fifth gate structures aligned with a first segment and a second segment of the third gate structure, respectively;
a first active structure extending along a second lateral direction and overlaid by respective first portions of the first to fourth gate structures, the second lateral direction perpendicular to the first lateral direction;
a second active structure extending along the second lateral direction and overlaid by respective second portions of the first to fourth gate structures; and
a third active structure extending along the second lateral direction and overlaid by respective third portions of the third and fifth gate structures.