CPC G11C 11/2255 (2013.01) [G11C 11/4085 (2013.01); G11C 11/4097 (2013.01)] | 14 Claims |
1. An in-memory computing apparatus, comprising:
a memory control circuit;
a memory array coupled to the memory control circuit, wherein the memory control circuit controls data access of the memory array, and the memory array comprises:
a shifted weight storage area storing a plurality of shifted weight values, and providing a plurality of shifted sum-of-products according to a plurality of input signals provided by the memory control circuit through a plurality of first word lines;
a shift information storage area storing a number of shift units of the plurality of shifted weight values, and providing the number of shift units of the plurality of shifted weight values according to a plurality of control signals provided by the memory control circuit through a plurality of second word lines; and
a shift unit amount storage area storing a shift unit amount, and providing a column shift unit amount according to the plurality of input signals, wherein the column shift unit amount is equal to a sum-of-products of the plurality of input signals and the shift unit amount;
a sense circuit coupled to the memory array, sensing a plurality of current signals provided by the shifted weight storage area, the shift information storage area, and the shift unit amount storage area to obtain the plurality of shifted sum-of-products, the number of shift units of the plurality of shifted weight values, and the column shift unit amount; and
a shift restoration circuit coupled to the sense circuit, and restoring weight shift amounts of the plurality of shifted sum-of-products according to the number of shift units of the plurality of shifted weight values and the column shift unit amount to generate a plurality of restored sum-of-products.
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