US 11,657,119 B2
Hardware accelerated convolution
Swapnil P. Sakharshete, La Jolla, CA (US); Samuel Lawrence Wasmundt, La Jolla, CA (US); Maxim V. Kazakov, La Jolla, CA (US); and Vineet Goel, La Jolla, CA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Aug. 30, 2019, as Appl. No. 16/557,911.
Application 16/557,911 is a continuation in part of application No. 16/215,298, filed on Dec. 10, 2018, granted, now 11,030,095.
Prior Publication US 2020/0184002 A1, Jun. 11, 2020
Int. Cl. G06F 17/16 (2006.01); G06N 3/08 (2023.01)
CPC G06F 17/16 (2013.01) [G06N 3/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processing device, comprising:
memory configured to store data;
a processor configured to:
determine, based on convolutional parameters comprising padding parameters indicating whether n, h, w, c positions of an image space, of an image, along a height and width of the image space comprise padded data, a virtual general matrix-matrix multiplication (GEMM) space of a virtual GEMM space output matrix; and
generate, in the virtual GEMM space output matrix, a convolution result by matrix multiplying the data corresponding to a virtual GEMM space input matrix with the data corresponding to a virtual GEMM space filter matrix; and
convolutional mapping hardware configured to map, based on the convolutional parameters, x, y positions of the virtual GEMM space input matrix to the n, h, w, c positions of the image space using n, h, w, c memory addresses.