CPC G06F 13/4013 (2013.01) [G06F 13/4239 (2013.01)] | 12 Claims |
1. An Avalon-to-Axi4 bus conversion method, comprising:
in case that an Avalon bus is a streaming mode of the Avalon bus (Avalon_st bus), receiving Avalon_st bus data, performing a logical process on the Avalon_st bus data, and then outputting corresponding streaming mode of an Axi4 bus (Axi4_st bus) data; and
in case that the Avalon bus is a memory mapping mode of the Avalon bus (Avalon_mm bus), receiving a signal transmitted by each channel of the Avalon_mm bus, framing and storing the signal in asynchronous First Input First Output (FIFO), and in case that a device corresponding to an Axi4 bus is ready, reading the signal from the asynchronous FIFO, and outputting the signal to a corresponding channel of the Axi4 bus according to a timing relationship of the Axi4 bus;
wherein the performing a logical process on the Avalon_st bus data and then outputting the corresponding streaming mode of the Axi4_st bus data comprises:
assigning values of a data packet end marker, data validity identifier, and device ready-state identifier in the Avalon_st bus data to corresponding interfaces of an Axi4_st bus;
performing high-low bit logic negation in units of bytes on data in the Avalon_st bus data, and then assigning a value to the corresponding interface of the Axi4_st bus; and
obtaining a valid byte position based on an invalid byte position in the Avalon_st bus data, and assigning a value at the valid byte position to the corresponding interface of the Axi4_st bus.
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