US 11,656,993 B2
LBNs prefetching per CPU
Kevin James Wendzel, Rochester, MN (US)
Assigned to Western Digital Technologies, Inc., San Jose, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Jul. 5, 2022, as Appl. No. 17/857,224.
Application 17/857,224 is a division of application No. 16/748,790, filed on Jan. 21, 2020, granted, now 11,422,941.
Application 16/748,790 is a division of application No. 15/474,340, filed on Mar. 30, 2017, granted, now 10,565,115, issued on Feb. 18, 2020.
Prior Publication US 2022/0334974 A1, Oct. 20, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/0862 (2016.01)
CPC G06F 12/0862 (2013.01) [G06F 2212/602 (2013.01); G06F 2212/6026 (2013.01); G06F 2212/7201 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a memory system, the memory system comprising:
a first CPU;
at least one additional CPU;
a memory device coupled to both the first CPU and the at least one additional CPU; and
a controller coupled to the memory system, the controller configured to:
receive a first request from a host device to read a first data and a second request to read a second data from a memory device that is coupled to a plurality of CPUs, wherein a first CPU of the plurality of CPUs has a first cache storage and a second CPU of the plurality of CPUs has a second cache storage;
read the first data from the memory device using the first CPU;
read the second data from the memory device using the second CPU of the plurality of CPUs;
write the first data and the second data to the first cache storage of the first CPU;
read the first and second data from the first cache storage; and
deliver the first and second data to the host device.