| CPC G06F 12/0802 (2013.01) [G06F 2212/1024 (2013.01)] | 18 Claims |
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1. A memory device including;
a plurality of page buffers, storing an input data;
a plurality of memory planes coupled to the page buffers, a plurality of weights stored in the memory planes, based on received addresses of the memory planes, the memory planes performing bit multiplication on the weights and the input data in the page buffers in parallel to generate a plurality of bit multiplication results in parallel, the bit multiplication results stored back to the page buffers; and
at least one accumulation circuit coupled to the page buffers, for performing bit accumulation on the bit multiplication results of the memory planes in parallel or in sequential to generate a multiply-accumulate (MAC) operation result.
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