US 11,656,674 B2
Power consumption reduction circuit for GPUs in server, and server
Peng Wang, Jiangsu (CN); Shichao Cheng, Jiangsu (CN); Longling Sun, Jiangsu (CN); Wenyu Liu, Jiangsu (CN); and Mingyang Ye, Jiangsu (CN)
Assigned to INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD., Jiangsu (CN)
Appl. No. 17/791,310
Filed by SUZHOU INSPUR INTELLIGENT TECHNOLOGY CO., LTD., Jiangsu (CN)
PCT Filed Sep. 24, 2020, PCT No. PCT/CN2020/117277
§ 371(c)(1), (2) Date Jul. 7, 2022,
PCT Pub. No. WO2021/208360, PCT Pub. Date Oct. 21, 2021.
Claims priority of application No. 202010300844.3 (CN), filed on Apr. 16, 2020.
Prior Publication US 2023/0035371 A1, Feb. 2, 2023
Int. Cl. G06F 1/3234 (2019.01); G06T 1/20 (2006.01); G06F 1/3206 (2019.01); G06F 1/26 (2006.01); G06F 1/324 (2019.01)
CPC G06F 1/3278 (2013.01) [G06T 1/20 (2013.01); G06F 1/26 (2013.01); G06F 1/324 (2013.01); G06F 1/3206 (2013.01); Y02D 10/00 (2018.01)] 15 Claims
OG exemplary drawing
 
1. A power consumption reduction circuit for Graphics Processing Units (GPUs) in a server, comprising:
a frequency reduction control chip connected with a Power Supply Unit (PSU) in the server and a Power Break (PWRBRK) pin of each of the GPUs in the server respectively, wherein the frequency reduction control chip is configured to, after receiving an overpower alarm signal generated by the PSU, generate a frequency reduction control signal to the PWRBRK pin of each of the GPUs so as to start a frequency reduction operation of each of the GPUs;
a switch chip connected with an output end of the frequency reduction control chip and the PWRBRK pin of each of the GPUs respectively; and
a control circuit connected with a channel control terminal of the switch chip, wherein the control circuit is configured to determine a target GPU in need of frequency reduction processing from each of the GPUs according to a comparison relationship between overall power consumption of the server and rated power of the PSU, and control the switch chip to enable a transmission channel between the frequency reduction control chip and the target GPU so as to output the frequency reduction control signal to the PWRBRK pin of the target GPU to start the frequency reduction operation of the target GPU.