US 11,656,671 B2
Negotiating a transmit wake time
Aviad Wertheimer, Tsur Hadassah (IL); and Robert Hays, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 20, 2022, as Appl. No. 17/725,211.
Application 17/725,211 is a continuation of application No. 17/087,891, filed on Nov. 3, 2020, granted, now 11,340,681.
Application 17/087,891 is a continuation of application No. 16/542,193, filed on Aug. 15, 2019, granted, now 10,860,079, issued on Dec. 8, 2020.
Application 16/542,193 is a continuation of application No. 15/236,463, filed on Aug. 14, 2016, granted, now 10,386,908, issued on Aug. 20, 2019.
Application 15/236,463 is a continuation of application No. 14/504,654, filed on Oct. 2, 2014, granted, now 9,454,204, issued on Sep. 27, 2016.
Application 14/504,654 is a continuation of application No. 13/489,434, filed on Jun. 5, 2012, granted, now 8,898,497, issued on Nov. 25, 2014.
Application 13/489,434 is a continuation of application No. 12/381,811, filed on Mar. 17, 2009, granted, now 8,201,005, issued on Jun. 12, 2012.
Prior Publication US 2022/0244771 A1, Aug. 4, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/32 (2019.01); G06F 1/3203 (2019.01); G06F 1/3209 (2019.01)
CPC G06F 1/3203 (2013.01) [G06F 1/3209 (2013.01); Y02D 30/00 (2018.01)] 20 Claims
OG exemplary drawing
 
1. An Ethernet physical layer transceiver (PHY) circuitry for use in a duplex frame communication with a remote link partner, the Ethernet PHY circuitry also to communicate, when the Ethernet PHY circuitry is in operation, with a local medium access controller (MAC) circuitry, the Ethernet PHY circuitry comprising:
a physical coding sublayer (PCS) circuitry for use in communicating with the local MAC circuitry;
a transmitter circuitry and a receiver circuitry for use in the duplex frame communication;
wherein, when the Ethernet PHY circuitry is in the operation:
the transmitter circuitry, during at least one negotiation with the remote link partner, is to transmit frame information for use in determining, at least in part, (1) at least one power saving capability of the Ethernet PHY circuitry associated, at least in part, with the duplex frame communication, and (2) a requested wait time that the transmitter circuitry is requesting to wait, prior to resuming data transmission to the remote link partner, following a temporary halt of the data transmission associated, at least in part, with the at least one power saving capability;
the transmitter circuitry is to wait a negotiated wait time, prior to the resuming of the data transmission, following the temporary halt of the data transmission associated, at least in part, with the at least one power saving capability of the Ethernet PHY circuitry, the negotiated wait time being determined based, at least in part, upon the requested wait time and another requested wait time, the another requested wait time to be requested during the at least one negotiation by the remote link partner;
the at least one power saving capability of the Ethernet PHY circuitry is to be implemented in accordance with at least one software-programmable power saving policy;
the at least one software-programmable power saving policy (1) corresponds to at least one of a plurality of power saving modes of operation, and (2) is associated with at least one entry time to enter and/or at least one exit time to exit the at least one of the plurality of power saving modes of operation; and
at least certain of the plurality of power saving modes of operation correspond to different respective wake latencies and different respective power savings.