CPC G01R 31/3177 (2013.01) [G01R 31/31723 (2013.01); G01R 31/31725 (2013.01); G01R 31/31727 (2013.01); G01R 31/318533 (2013.01)] | 3 Claims |
1. A device comprising:
a first access port compliant with a first protocol associated with IEEE 1149.1, wherein the first access port includes:
a serial instruction register;
a serial data register;
a serial input;
a serial output;
a clock input; and
a control input;
a second access port compliant with a second protocol that differs from the first protocol, wherein the second access port includes:
a serial register coupled to at least one of a parallel data receiving circuit and a parallel data providing circuit;
a serial input;
a serial output;
a clock input; and
a control input;
an access port selector compliant with a third protocol that differs from the first protocol and the second protocol, wherein the access port selector includes:
a control input;
a clock input;
a first enable output; and
a second enable output;
a first gating circuit including:
a first input coupled to a control input;
a second input coupled to the first enable output of the access port selector; and
an output coupled to the control input of the first access port;
a second gating circuit including:
a first input coupled to the control input;
a second input coupled to the second enable output of the access port selector; and
an output coupled to the control input of the second access port; and
an external control input to the device coupled to:
the control input of the access port selector;
the control input to the first gating circuit; and
the control input of the second gating circuit.
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